1. Technical Field of the Invention
The present invention relates to microelectronics, and especially to integrated circuits comprising photodiodes of the floating substrate type.
2. Description of Related Art
Image sensors based on semiconductor components advantageously rely on the principle of photons being converted into electron/hole pairs in silicon. More precisely, the charges created in photosensitive regions are stored in the photodiode and are then read by an electronic system. This electronic system, which controls the photodiode, comprises in particular a read transistor for converting the charges stored in the photodiode into an electrical quantity.
The present invention applies advantageously but without limitation to CMOS image sensors and more particularly to VMIS sensors (Vth modulation image sensors) which are image sensors that rely on the modulation of the threshold voltage of an MOS transistor. The reader may refer on this subject to the article by Takashi Miida et al., “A 1.5 Mpixel Imager with Localized Hole Modulation Method”, ISSCC Dig. Tech. Pap., pp. 42-43, July 2002, the disclosure of which is hereby incorporated by reference.
This type of CMOS transistor consists of a buried photodiode and an MOS transistor, owing to the fact that its substrate is a floating substrate, that is to say its potential can only be reached via an electrode, for example. This floating substrate acts as a charge storage region during charge integration, that is to say when the incident light generates electron/hole pairs in the photosensitive regions.
Another type of transistor to which the invention advantageously applies is a transistor of the BCMD (bulk charge modulated device) type. This transistor includes, in particular, a storage area or pocket located beneath the gate of the transistor so as to make it easier to integrate the charges. These transistors are described specifically in the article by Jaroslav Hynecek entitled “BCMD—an improved photosite structure for high density image sensors”, IEEE Transactions On Electron Devices, Vol. 38, No. 5, May 1991, the disclosure of which is hereby incorporated by reference.
Conventionally, the operation of an integrated circuit that includes a photodiode associated with a read transistor operates in three separate phases, namely an integration phase, a read phase and a reset phase.
During the integration phase, the charges photogenerated in the photosensitive regions of the photodiode by the incident photons are attracted into and then stored in the floating substrate and more particularly at the pocket lying beneath the gate of the transistor in the case of BCMD-type transistors, for example. This charge accumulation results in a variation in the threshold voltage of the MOS transistor, which is measured during the read phase, by connecting the transistor in what is called a “source follower” mode and by reading the source bias.
During the reset phase, the accumulated charges are expelled from the floating substrate into the bulk of the photodiode via a buried layer, included in the layer of the photodiode that lies between the floating substrate and the bulk. Said buried layer constitutes a barrier for the charges photogenerated during the first two phases.
After the reset phase, the floating substrate and the buried layer are then completely drained of its charges.
To optimize the reset phase, the aim is to obtain a maximum voltage amplitude between the bulk and the upper layer of the photodiode. To do this, voltages of around 6 to 8 volts are applied both to the gate and to the drain, that is to say voltages that are very much higher than the standard bias voltages generally used at the present time in CMOS technology, which vary between 0 and 3.3 volts.
This is because, since the buried layer is connected to the drain, the buried layer bias tends to align with the drain bias. In addition, in order to direct the charges into the photodiode bulk during the reset phase, it is necessary to use relatively high voltages and also the doping levels and the thickness of the buried layer must be controlled very precisely during production, something which is not very easily achievable.
Moreover, during the integration phase, the floating substrate bias must be able to reach a minimum value so that the potential difference between a floating substrate drained of charges and full of charges, called the “voltage swing”, is as high as possible.
Consequently, to favor the integration and read phases and thus optimize the electronic performance of the circuit (for example, the dynamic range of the output voltage of the circuit), it is preferable for the pocket to be highly doped.
In contrast, a low pocket doping level favors the reset phase.
There is a need to provide a solution to these problems.